1. Field of the Invention
The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device in which a source/drain region occupies a reduced area so as to decrease the parasitic capacitance and parasitic resistance of the source/drain region, as well as a method for producing the same.
2. Description of the Related Art
In general, smaller insulation gate type field effect transistors (FETs) become more susceptible to problems such as fluctuation in the threshold voltage due to variation in the gate length caused by processing variations, an increased off-leak current due to deterioration of subthreshold characteristics, and deterioration of transistor characteristics due to short channel effects, e.g., so-called punch-through.
One method for solving such problems has been to reduce the junction depth of the source/drain regions adjoining a channel region of a transistor. A reduced junction depth can be realized by, for example, a structure in which source/drain regions (stacked diffusion layers) are stacked on both sides of a gate electrode so as to be located above the-channel region via gate electrode lateral wall insulation films.
FIGS. 22A, 22B, and 22C are cross-sectional views illustrating-steps of a conventional method for forming stacked diffusion layers.
As shown in FIG. 22A, a gate electrode 1005 whose upper face and side walls are covered with an insulation film 1006 is formed upon a semiconductor wafer 1001, with a gate insulation film 1004 interposed therebetween. The semiconductor wafer 1001 generally includes an active region 1003 (composed of a silicon substrate) and device separation regions 1002 (composed of a silicon oxide film).
Next, as shown in FIG. 22B, a selective epitaxial growth method is used to grow a silicon film 1007 exclusively in regions (source/drain regions) where the silicon surface is exposed, thereby forming stacked diffusion layer regions (which are composed of a semiconductor) in the source/drain regions. A selective epitaxial growth method is disclosed in Japanese Laid-open Publication No. 61-196577.
As shown in FIG. 22C, an interlayer insulation film 1008 is formed, and upper wiring 1010 is coupled to the source/drain regions 1007 via contact wires 1009.
After the silicon film (epitaxial silicon, polycrystalline silicon, etc.) has been formed above the channel region, impurity ions are implanted so as to form the source/drain regions. By thus implanting impurity ions in the stacked silicon films which are located above the channel region, it becomes possible to reduce the junction depth of the source/drain region impurity diffusion layers relative to the channel region of the transistor. As a result, so-called short channel effects can be effectively prevented.
The source/drain regions 1007 extend from the gate electrode 1005 to the device separation regions 1002 along a direction X-Xxe2x80x2 (commonly referred to as the xe2x80x9cgate length directionxe2x80x9d) which is perpendicular to the longitudinal direction of the gate electrode. When contact holes are formed in such source/drain regions 1007, the length of each source/drain region 1007 will be determined as follows.
FIG. 15 is a diagram illustrating the relationship between a gate electrode, an active region, and contact holes. A positioning margin p is provided between the gate electrode and each contact hole. Each contact hole has a width o. The contact holes are positioned with respect to the source/drain regions with a margin q as illustrated in FIG. 15. It will be appreciated that the length of each source/drain region 1007 cannot become smaller than p+o+q in the semiconductor device illustrated in FIG. 22C.
Thus, it is difficult to reduce the area occupied by the source/drain regions in accordance with the semiconductor device disclosed in Japanese Laid-open Publication No. 61-196577.
A semiconductor device having a device separation region and an active region according to the present invention includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region, wherein the active region is in contact with the gate oxide film at a first face, a portion of the source/drain regions being located above the first face; and wherein the electrode is in contact with the source/drain region at a second face, the second face constituting an angle with respect to the first face.
In one embodiment of the invention, the second face is substantially rugged.
In another embodiment of the invention, a portion of the source/drain region partially covers the device separation region.
In still another embodiment of the invention, the height of the source/drain region as measured from the first face along a direction perpendicular to the first face increases toward the gate electrode.
In still another embodiment of the invention, the second face has a curved profile.
In still another embodiment of the invention, a portion of a contact hole for interconnecting the source/drain region and upper wiring is present on the surface of the source/drain region.
In still another embodiment of the invention, a distance between an end of the gate electrode and an end of the contact hole that is located away from the gate electrode in a cross section extending along a direction perpendicular to a longitudinal direction of the gate electrode and through a center of the contact hole is larger than a distance between the end of the gate electrode and an interface between the active region and the device separation region.
In still another embodiment of the invention, a width of the contact hole as measured in a cross section extending along a direction perpendicular to a longitudinal direction of the gate electrode and through a center of the contact hole is larger than a distance between an end of the gate electrode and an interface between the active region and the device separation region.
In still another embodiment of the invention, in a cross section extending along a direction perpendicular to a longitudinal direction of the gate electrode, a distance between an end of the gate electrode and an interface between the active region and the device separation region is smaller than a width of the gate electrode, the width of the gate electrode defining a gate length of the semiconductor device.
In still another embodiment of the invention, a diffusion coefficient of an impurity within a stacked layer constituting the source/drain region is larger than a diffusion coefficient of an impurity within the semiconductor substrate.
In still another embodiment of the invention, the diffusion coefficient of the impurity within the stacked layer is about 2 to about 100 times as large as the diffusion coefficient of an impurity within the semiconductor substrate.
In still another embodiment of the invention, the stacked layer includes polycrystalline silicon.
In still another embodiment of the invention, the polycrystalline silicon includes columnar crystals.
In still another embodiment of the invention, the polycrystalline silicon has a grain size of about 50 nm or less.
In still another embodiment of the invention, a surface of the gate electrode and the source/drain region is covered by a two-layer film, the two-layer film including a polycrystalline silicon film and a refractory metal silicide film.
In still another embodiment of the invention, a junction depth of the source/drain region from the first face is about 0.8 to about 2 times as large as a width of the gate electrode lateral wall insulation film.
In another aspect of the invention, there is provided a method for producing a semiconductor device having a device separation region and an active region, the method including the steps of: forming the device separation region on a silicon substrate from a material which substantially withstands silicon etching; sequentially forming a gate insulation film, a gate electrode, and a gate electrode lateral wall insulation film; coating a polycrystalline silicon film having a thickness which is larger than a distance between the gate electrode and the device separation region along a direction perpendicular to a longitudinal direction of the gate electrode: and performing an anisotropic etching until the polycrystalline silicon film above the gate electrode is substantially removed.
In one embodiment of the invention, the method further includes an ion implantation step of introducing an impurity to form the source/drain region, the impurity becoming one of a donor and an acceptor, and wherein the gate electrode is formed by the introduction of the impurity to become the one of a donor and an acceptor; and the introduction of the impurity to become the one of a donor or an acceptor for the gate electrode and the source/drain region is performed simultaneously by ion implantation.
Alternatively, the method for producing a semiconductor device according to the present invention includes the steps of: forming a device separation region on a silicon substrate from a material which substantially withstands silicon etching; sequentially forming a gate insulation film, a gate electrode, and a gate electrode lateral wall insulation film; coating a polycrystalline silicon film; performing an anisotropic etching until the polycrystalline silicon film above the gate electrode is substantially removed; and removing a portion of the polycrystalline silicon film, the polycrystalline silicon film having been formed on a lateral wall of the gate electrode with the gate electrode lateral wall insulation film being interposed between the polycrystalline silicon film and the lateral wall of the gate electrode.
(1) In accordance with the above constitution, the parasitic resistance of the source/drain region can be reduced. The surface of the source/drain region becomes more elevated with respect to the active region on the semiconductor substrate toward the gate electrode. As a result, when an impurity doping for the source/drain region is performed by ion implantation, the junction depth becomes smaller toward the gate electrode, thereby effectively preventing short-channel effects, which would otherwise become problematic when constructing a downsized semiconductor device.
Since it is possible to secure a large surface area relative to the area occupied by the source/drain region according to the present invention, the contact area between the source/drain region and upper wiring can be increased, thereby reducing the contact resistance relative to the occupied area.
In the case of a configuration employing a salicide (i.e., self aligned silicide), the surface area which is converted into a silicide is increased relative to the occupied area according to the present invention, thereby achieving low resistance. Moreover, failure of silicidation of fine wiring due to hindrance of reaction can be alleviated, which has conventionally been a problem in silicidation reactions.
Moreover, the constitution according to the present invention obviates any vertical protrusion at a gate position, whereby various problems associated with such vertical protrusions of gates during semiconductor device manufacture are solved. For example, the problem of an insufficient etching ratio between a vertical protrusion and an underlying stopper layer during etching, e.g., self-aligned contact (SAC) process, can be prevented so as to facilitate etching. In addition, it is easy to flatten the interlayer insulation film above the gate portion. Since the active region is not exposed to the atmosphere after the source/drain regions are formed, the active region is prevented from being damaged during etching and/or contamination during ion implantation.
(2) According to the present invention, the surface of each source/drain region exhibits a curved and/or slanted profile in a cross section taken along the direction perpendicular to the longitudinal direction of the gate electrode. As a result, the surface area of each source/drain region of the semiconductor device (relative to the area which is occupied by the source/drain region) can be more effectively increased according to the present invention than in conventional structures incorporating source/drain regions having a linear profile.
(3) According to the present invention, at least a portion of a contact hole for coupling the surface of the source/drain region to wiring is present on the surface of the source/drain region. In other words, the diameter of the contact hole aperture can be prescribed to be larger than the length of a portion of the active region from an end of the gate to the device separation region in a cross section extending along a direction perpendicular to a longitudinal direction of the gate electrode. As a result, the diameter of the contact aperture can be increased, thereby facilitating contact hole formation.
In conventional structures, contact holes need to be provided on the source/drain region surface, so that the diameter of each contact needs to be smaller than the width of each source/drain region, thereby making difficult the process of making contact apertures. Furthermore, in accordance with the device structure of the present invention, a sufficient contact area can be secured by providing a contact hole which has a longer dimension along the longitudinal direction of the gate electrode than the dimension along a direction perpendicular to the longitudinal direction of the gate electrode.
(4) In accordance with an embodiment of the invention, the distance between an end of the gate electrode and an end of the contact hole that is located away from the gate electrode in a cross section extending along the direction perpendicular to the longitudinal direction of the gate electrode and through the center of the contact hole is larger than the distance between the end of the gate electrode and an interface between the active region and the device separation region.
As a result, it is possible to provide a large contact hole without increasing the source/drain area, thereby achieving facility in the contact hole formation and reduction in the junction capacitance, which depends on the source/drain junction area.
(5) In accordance with an embodiment of the invention, the width of the contact hole as measured in a cross section extending along the direction perpendicular to the longitudinal direction of the gate electrode and through the center of the contact hole is larger than the distance between an end of the gate electrode and an interface between the active region and the device separation region.
As a result, it is possible to maximize the contact area between the contact holes and the source and drain, while minimizing the source/drain area. Thus, the contact resistance can be reduced.
(6) In accordance with an embodiment of the invention, in a cross section extending along the direction perpendicular to the longitudinal direction of the gate electrode, the distance between an end of the gate electrode and an interface between the active region and the device separation region is smaller than the width of the gate electrode (i.e., the gate length of an MIS (metal insulator semiconductor) type semiconductor device).
As a result, the area occupied by the device can be minimized, and the parasitic junction capacitance at the source/drain region can also be minimized.
(7) In accordance with an embodiment of the invention, the diffusion coefficient of an impurity within a stacked layer constituting the source/drain region is larger than a diffusion coefficient of an impurity within the semiconductor substrate.
As a result, when performing a heat treatment for diffusing and activating an impurity, the diffusion occurs very rapidly down to the interface between the stacked layer and the semiconductor substrate, but only slowly into the silicon substrate. As a result, the junction depth of the source/drain regions from the interface between the stacked layer and the semiconductor substrate is less likely to be affected by variation in the height of the stacked regions, thereby making it possible to produce a shallow junction with much controllability.
(8) In accordance with an embodiment of the invention, the diffusion coefficient of an impurity within the stacked layer is about 2 to about 100 times as large as the diffusion coefficient of an impurity within the semiconductor substrate.
As a result, the junction depth of a portion the source/drain region from the interface between the stacked layer and the semiconductor substrate is less likely to be affected by variation in the height of the stacked regions, thereby making it possible to produce a shallow junction with much controllability.
(9) In accordance with an embodiment of the invention, the stacked layer constituting the source/drain region stacked above the semiconductor substrate is composed essentially of polycrystalline silicon.
Since polycrystalline silicon films are commonly used in the manufacture of semiconductor devices, there is no need to introduce new apparatuses in the process or to determine any new set of process conditions. It is also unnecessary to use a large amount of hydrogen as in the case of employing a selective epitaxial growth apparatus. Thus, the apparatus which is required for manufacturing a semiconductor device according to the present invention occupies much less space than a selective epitaxial growth apparatus (which would require large size equipment for hydrogen removal).
(10) In accordance with an embodiment of the invention, the polycrystalline silicon are columnar crystals.
As a result, the diffusion of impurity occurs very rapidly within the polycrystalline silicon film, and an impurity which is doped into the polycrystalline silicon film can be allowed to diffuse into the silicon substrate with good controllability. The depth of the source/drain regions is less likely to be affected by variation in the height of the polycrystalline silicon, thereby making it possible to produce a shallow junction with much controllability.
(11) In accordance with an embodiment of the invention, the polycrystalline silicon has a grain size of about 50 nm or less.
By employing a polycrystalline silicon having such a small grain size, it becomes possible to obtain a large diffusion coefficient relative to the diffusion coefficient within the semiconductor substrate. It is also possible to minimize the variation in the width of the polycrystalline silicon side walls due to the grains of polycrystalline silicon during etching back.
(12) In accordance with an embodiment of the invention, the gate electrode and the source/drain stacked layer are composed essentially of a two-layer film including a polycrystalline silicon film and an overlying refractory metal silicide film.
As a result, it is possible to realize a very low-resistance contact even without increasing the contact area between the source/drain region and upper wiring. Furthermore, since a silicide film exists near the channel region, it is possible to minimize the parasitic resistance despite a small source/drain junction area, thereby improving the driving current performance of the device. It also becomes possible to utilize the silicide layer as an etching stopper layer during contact hole etching.
(13) A method for producing an MIS type semiconductor device formed on a semiconductor substrate including a device separation region and an active region according to the present invention includes the steps of: forming the device separation region on a silicon substrate from a material which substantially withstands silicon etching; sequentially forming a gate insulation film, a gate electrode, and a gate electrode lateral wall insulation film; coating a polycrystalline silicon film having a thickness which is larger than the distance between the gate electrode and the device separation region along the direction (gate length direction) perpendicular to the longitudinal direction of the gate electrode; and performing an anisotropic etching until the polycrystalline silicon film above the gate electrode is substantially removed.
Specifically, in accordance with the method for producing a semiconductor device of the present invention, a polycrystalline silicon film having a thickness which is larger than the distance between the gate electrode and the device separation region (i.e., the source/drain region width) and an anisotropic etch back process is performed. Because of the deposition of the polycrystalline silicon film having a thickness larger than the distance between the gate electrode and the device separation region (i.e., the source/drain region width), the silicon substrate is prevented from being exposed and/or damaged by an anisotropic etch-back process. By forming the stacked layers by the sides of the gate electrode lateral walls through an anisotropic etch-back process, it is ensured that the end of each stacked layer extends at least partially on a device separation region, which in itself is formed of a material which substantially withstands silicon etching. Since merely performing the above etch-back process may result in the source region and the drain region short-circuiting with each other, it is necessary to separate the stacked region of polycrystalline silicon (formed on the lateral walls of the gate electrode) into discrete source/drain regions.
(14) Alternatively, a method for producing a semiconductor device of the present invention includes the steps of: forming a device separation region on a silicon substrate from a material which substantially withstands silicon etching; sequentially forming a gate insulation film, a gate electrode, and a gate electrode lateral wall insulation film; coating a polycrystalline silicon film; performing an anisotropic etching until the polycrystalline silicon film above the gate electrode is substantially removed; and removing a portion of the polycrystalline silicon film, the polycrystalline silicon film having been formed on a lateral wall of the gate electrode with the gate electrode lateral wall insulation film being interposed between the polycrystalline silicon film and the lateral wall of the gate electrode.
As a result, it is possible to form source/drain regions which are stacked above the gate electrode in a self-aligned manner.
(15) Yet another method for producing a semiconductor device of the present invention includes an ion implantation step of introducing an impurity to form the source/drain region, the impurity becoming a donor or an acceptor (more precisely, the doped region becomes a donor or an acceptor). As described above, the stacked layers of source/drain regions (which are stacked above the semiconductor substrate) are composed of a material such that the diffusion coefficient of an impurity within the stacked layers is larger than the diffusion coefficient of an impurity within the semiconductor substrate. As a result, even by simultaneously performing the impurity doping for the gate electrode and the impurity doping for the source/drain regions, it is possible to produce a device which can prevent the depletion of the gate electrode and/or the penetration of the impurity into the channel region, and which does not have an offset configuration (i.e., a configuration in which the source/drain regions do not substantially reach the channel region in the lateral direction due to insufficient diffusion).
(16) In accordance with an MIS type semiconductor device according to the present invention, source/drain regions are provided so as to adjoin gate electrode lateral wall insulation films flanking the gate electrode and extend above an active region surface, in such a manner that the junction depth of the source/drain region from the first face is about 0.8 to about 2 times as large as the width of the gate electrode lateral wall insulation film.
Thus, the invention described herein makes possible the advantages of (1) providing a semiconductor device whose source/drain regions occupy relatively small areas; and (2) providing a method for producing the same.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.